The invention relates to a device and to a method for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states.
A prominent example for resistive memory cells having a plurality of programmable levels or states are Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM). PCM is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
PCM is a promising and advanced emerging non-volatile memory technology mainly due to its excellent features including low latency, high endurance, long retention and high scalability. PCM may be considered a prime candidate for Flash replacement, embedded/hybrid memory and storage-class memory. Key requirements for competitiveness of PCM technology may be multi-level cell functionality, in particular for low cost per bit, high-speed read/write operations, in particular for high bandwidth and high endurance. Multilevel functionality, i.e. multiple bits per PCM cell, may be a way to increase storage capacity and thereby to reduce cost.
Multi-level PCM is based on storing multiple resistance levels between a lowest (SET) and a highest (RESET) resistance value. Multiple resistance levels or levels correspond to partial-amorphous and partial-crystalline phase distributions of the PCM cell. Phase transformation, i.e. memory programming, may be enabled by Joule heating. In this regard, Joule heating may be controlled by a programming current or voltage pulse. Storing multiple resistance levels in a PCM cell is a challenging task.
For example, in H.-S. P. Wong et al., Proc. IEEE, 2010 it is described that the multiple states or levels in a PCM cell are created by varying the programming power, thus creating different crystalline and amorphous fractions within the cell. Further according to H.-S. P. Wong et al., Proc. IEEE, 2012, in metal-oxide resistive memory devices, multiple states may correspond to variations in the gap between conductive oxygen-vacancy filaments and the electrodes.
As mentioned above, in resistive memory, the fundamental storage unit (referred to generally herein as the “cell”) can be set to a number of different states which exhibit different electrical resistance characteristics. Information is recorded by exploiting the different states to represent different data values. To read recorded data, cell-state is detected via measurements which exploit the differing resistance characteristics to differentiate between possible cell-states. A variety of semiconductor memory technologies employ these basic principles for data storage. Examples include oxide-based memory such as resistive RAM and memristor memory, ionic-transport-based memory, and phase-change memory. The following discussion will focus on phase-change memory (PCM) as a particularly promising technology for future non-volatile memory chips. It is to be understood however, that PCM is only an illustrative application for the invention to be described which can be similarly applied to other resistive memory technologies.
Phase-change memory exploits the reversible switching of certain chalcogenide materials between at least two states with different electrical resistance. In so-called “single-level cell” (SLC) PCM devices, each cell can be set to one of two states, crystalline and amorphous, by application of heat. Each SLC cell can thus store one bit of binary information. However, to satisfy market demand for ever-larger memory capacity and reduce cost per bit, storage of more than one bit per cell is required. To achieve this, it is necessary that a cell can be set to s states where s>2, and that these states can be distinguished on readback via the cell resistance characteristics. Multi-level cell (MLC) operation has been proposed for PCM cells whereby each cell can be set to one of s>2 resistance levels, each corresponding to a different cell state. MLC operation is achieved by exploiting partially-amorphous states of the chalcogenide cell. Different cell states are set by varying the effective volume of the amorphous phase within the chalcogenide material. This in turn varies cell resistance.
To write data to a PCM cell, a voltage or current pulse is applied to the cell to heat the chalcogenide material to an appropriate temperature to induce the desired cell-state on cooling. By varying the amplitude of the voltage or current pulses, different cell-states can be achieved. Reading of PCM cells can be performed using cell resistance to distinguish the different cell-states. The resistance measurement for a read operation is performed in the sub-threshold region of the current-versus-voltage (IN) characteristic of the cell, i.e. in the region below the threshold switching voltage at which a change in cell-state can occur. The read measurement can be performed in a variety of ways, but all techniques rely fundamentally on either voltage biasing and current sensing, or current biasing and voltage sensing. In a simple implementation of the current-sensing approach, the cell is biased at a certain constant voltage level and the resulting cell current is sensed to provide a current-based metric for cell-state. U.S. Pat. No. 7,426,134 B2 discloses one example of a current-sensing technique in which the bias voltage can be set to successive higher levels, and the resulting cell-current compared to successive reference levels, for detecting the different cell-states. US Patent Application Publication No. 2008/0025089 discloses a similar technique in which the cell current is simultaneously compared with different reference levels. In the alternative, voltage-sensing approach, a constant current is passed through the cell and the voltage developed across the cell is sensed to provide a voltage-based metric for cell-state.
Reading of MLC cells is particularly challenging as the read operation involves distinguishing fine differences in cell resistance via the current/voltage measurements. Compared to SLC operation, these fine differences are more readily affected by random noise fluctuations and drift over time, resulting in errors when retrieving stored data. To counteract this loss of data integrity associated with MLC memory, new cell-state metrics, beyond simple resistance, have been proposed. The copending European Patent Application No. 10174613.9, filed 31 Aug. 2010, discloses a particularly promising metric which is based on the sub-threshold slope of the I/V characteristic of the cell. For example, the metric may be based on the difference between two read measurements of the same cell. This type of metric is less sensitive to noise and drift. In certain embodiments of this measurement technique, the metric is essentially a voltage based metric in the sense that it calls for the measurement of cell voltages (or cell voltage differences) at given bias currents. In general, voltage-based metrics are considered advantageous over current-based metrics, showing less drift over time, less susceptibility to noise, better SNR (signal-to-noise ratio), and allowing more intermediate levels to be packed into one cell. However, the conventional technique for obtaining voltage-based metrics, using current biasing and voltage sensing, is undesirably slow as explained above. This speed penalty associated with the conventional voltage measurement technique means that there is a fundamental conflict between the requirement for a fast random access of the memory and the need for voltage-based metrics supporting high density MLC memory.
Recapitulating, the readout of the cell state may be done via a current-based metric (see U.S. Pat. No. 7,426,134, US 2008/0239833, US 2008/0025089, and US 20070140029) or via a voltage-based metric (see US 2012/0307554; G. Close, C. Hagleitner, A. Pantazi, N. Papandreou, C. Pozidis and A. Sebastian, Cell-state determination in phase-change memory, US patent application filed under CH920100091US1, United States 2010; US 2008/0165570; US 20080316803; and US 2012/0314481).